1. Field of the Invention
The invention in general relates to the design and fabrication of ferroelectric memories, and more particularly to memory architecture that includes a shunt across the ferroelectric capacitor in the memory cell which prevents undesirable switching of the ferroelectric material.
2. Statement of the Problem
Ferroelectric memories have been known for many years and offer many advantages over other memories. See U.S. Pat. No. 5,561,397, issued Oct. 1, 1996 to Takashi Mihara et al., for example. One of the most common and commercially successful ferroelectric memory designs utilizes a memory cell comprising a ferroelectric capacitor, one electrode of which is connected to a transistor, and the other electrode of which is connected to a line, conventionally called the plate line. The design and operation of a memory of this type is similar to the DRAM, thus these memories are commonly referred to as FeRAMs. There is at least one important difference between a DRAM and an FeRAM: a "read voltage" must be placed across the ferroelectric memory to read it. This difference has resulted in significant difficulties in designing an FeRAM that is as fast, failure resistant and dense as a conventional DRAM. See, for example, U.S. Pat. No. 5,406,510 issued Apr. 11, 1995 to Takashi Mihara et al.
One solution to the need for applying a voltage across the FeRAM to read it, has been to hold the plate line at a fixed (constant) voltage, usually equal to 1/2 the supply voltage. See U.S. Pat. No. 5,406,510 referenced above as well as U.S. Pat. No. 5,038,323 issued to Leonard J. Schwee on Aug. 6, 1991. In these designs the same plate line is connected to all or at least a portion of all memory cells, and thus is referred to as a common or cell plate line. The plate line is held at a constant voltage, which is 1/2 the supply voltage, Vcc. A problem with this design is that the electrical node between the capacitor and the transistor, though isolated from the rest of the circuit, tends to lose charge through various leakage paths such that the voltage on the node reaches a level different from that of the plate line. This is essentially a result of the fact that reversed-biased diodes and "off" MOSFETs have significant leakage in comparison to the leakage through the ferroelectric capacitor itself. The zero voltage on the node between the transistor and capacitor, which we will call the TC node herein, and the constant 1/2 Vcc voltage on the plate line results in a voltage, Vf, being developed across the ferroelectric capacitor at times when it is not being written to or read from, which voltage can cause the ferroelectric capacitor to switch, destroying the data held in the memory.
Another solution to the need to apply a voltage across the FeRAM to read it, is to pulse the common plate line only during certain portions of the read/write cycle. See for example, U.S. Pat. No. 4,873,664 issued Oct. 10, 1989 to S. Sheffield Eaton and Tatsumi Sumi et al., "A 256 kb Nonvolatile Memory at 3 V and 100 ns", in ISSCC Digest of Technical Papers, pp. 268-269, February 1994. In both these designs, the common plate line has a relatively large capacitance, and thus relatively large access time and a relatively slow memory. In addition, in the Eaton reference, the memory cell layout requires that adjacent rows of memory cells have unique plate lines, that is, if the plate lines are shared between rows, the deselected rows are sufficiently disturbed during the read or write cycles of adjacent rows, then the information in these shared but deselected rows is destroyed. The unique plate line for each row increases the area required by each row of memory cells. In the Sumi reference, the plate line is shared between two adjacent rows, however, only one of the rows is selected. One electrode of each ferroelectric capacitor in the deselected row receives the plate pulse. Because of a parasitic capacitance of the internal TC node in the cell structure, the internal TC node acts as a small capacitor in series with the large ferroelectric capacitor. Since the higher voltage drop is across the smaller capacitor in a series of capacitors, a significant voltage is developed on the TC node, which results in a small voltage existing for a relatively long time across each ferroelectric capacitor in the deselected cells, causing a disturb of its data state.
A solution to the above problems is to refresh the TC node to the 1/2 Vcc voltage of the plate line often enough that the voltage on the node never falls below a threshold voltage during periods that it is not being read or written to, which threshold voltage is close enough to the plate voltage to prevent disturbance of the memory state. See Hiroki Koike et al. "A 60-ns 1-Mb Nonvolatile Ferroelectric Memory with Non-Driven Cell Plate Line Write/Read Scheme", in ISSCC Digest of Technical Papers, pp. 368-369, February 1996. This results in a faster access time, but complicates the peripheral circuitry, consuming chip area and reducing the density of the memory. In addition, periods of time during normal memory operation must be set aside for the refresh to take place, thereby restricting memory access and introducing wait states. Thus, there remains the problem of how to design and fabricate an FeRAM that is as fast, failure resistant and dense as a conventional DRAM.
3. Solution to the Problem
The present invention provides, in a memory cell design that utilizes a shunt connected in parallel with the ferroelectric capacitor that significantly reduces the voltage across the capacitor at times when the capacitor is not being written to or read.
In a memory cell design that utilizes a plate line that is common to a plurality of different capacitors, the shunt is connected between the TC node and the common plate line.
In the preferred embodiment, adjacent TC nodes in the same row are shunted together, and there is only one shunt to the plate line every eight to thirty-two memory cells. This saves chip area.
The shunt may be passive or active. Examples of a passive shunt include a Schottky diode, back-to-back diodes, and a resistor having a resistance sufficiently high to permit the desired coercive voltage to be applied during the read and write cycles and sufficiently low that current flows to the TC node from the plate line at least as fast as it leaks off the TC node due to leakage. An example of an active shunt is a transistor.
If the shunt is a transistor, and the plate line is raised to the full supply voltage, the shunt line connected to the shunt transistor gate is boosted. This ensures that the full supply voltage will pass through the shunt.
The shunt system is formed in the same process steps as the cell transistor and the cell capacitor. Thus, no additional process steps are required to fabricate the shunt system.
The shunt system, for the most part, is located in areas of the chip that are redundant or contain other conventional cell parts, such as the bit line, at other levels in the layer structure. Thus, in general, the shunt system utilizes little additional chip area.
The invention provides a ferroelectric memory comprising: a transistor having a source/drain; a capacitor having a first electrode and a second electrode, the first electrode connected to the source/drain of the transistor to create a node that is isolated when the transistor is off; and a shunt system for directly electrically connecting the isolated node and the second electrode of the capacitor at a predetermined time to essentially equalize the voltages on the first and second electrodes of the capacitor during the predetermined time. Preferably, the shunt system comprises a shunt device selected from the group consisting of: a Schottky diode, a resistor, a pair of back-to-back diodes, and a shunt transistor. Preferably, the memory includes a supply voltage power source having an output voltage, the shunt transistor includes a gate, and the shunt system includes: a shunt line connected to the gate of the shunt transistor; and a signal generator for applying a shunt line signal to the shunt line, which signal is boosted above the voltage of the output voltage for at least a portion of the predetermined time. Preferably, the memory includes a plurality of memory cells, each of the memory cells including one of the isolated nodes, and the shunt system comprises: a first shunt device for directly electrically connecting the one of the isolated nodes in each of the cells to one of the isolated nodes in another of one of the cells during the predetermined time; and a second shunt device for directly electrically connecting at least one of the isolated nodes to the second electrode of the capacitor during the predetermined time. Preferably, there is one of the second shunt devices for every 2.sup.n of the memory cells, where n is an integer from zero to 10. Alternatively, there is one of the second shunt devices for every eight to thirty-two of the memory cells. Preferably, the memory further comprises a plate line for providing a voltage signal to the second electrode of the capacitor, and the shunt system comprises a shunt device for directly electrically connecting the isolated node and plate line. Preferably, the memory includes a memory cell having two of the transistors, two of the capacitors, and two of the isolated nodes, and the shunt system comprises a shunt device for directly electrically connecting the two isolated nodes. Preferably, the transistor and capacitor are part of a first memory cell in the memory, the memory includes a plurality of the memory cells and a plurality of word lines connected to the gates of the transistors in the memory cells, and the predetermined time includes essentially all of the cycles of the memory in which the word line connected to the first memory cell is not selected.
In another aspect the invention provides a ferroelectric memory cell comprising: a transistor having a source/drain; a capacitor having a first electrode and a second electrode, the first electrode connected to the source/drain of the transistor to create a node that is isolated when the transistor is off; and a shunt device for directly electrically connecting the isolated node and the second electrode of the capacitor at a predetermined time to essentially equalize the voltages on the first and second electrodes of the capacitor at the predetermined time. Preferably, the shunt device comprises a shunt device selected from the group consisting of: a Schottky diode, a resistor, and a pair of back-to-back diodes. Most preferably, the shunt device comprises a shunt transistor.
In a further aspect, the invention provides a ferroelectric memory cell comprising: a first transistor having a first source/drain and a second transistor having a second source/drain; a first capacitor having a first pair of electrodes and second capacitor having a second pair of electrodes, one of the first pair of electrodes connected to the first source/drain of the first transistor to create a first node that is isolated when the first transistor is off, one of the second pair of electrodes connected to the second source/drain of the second transistor to create a second node that is isolated when the second transistor is off; and a shunt device for directly electrically connecting the first isolated node and the second isolated node to essentially equalize the voltages on the nodes.
In still another aspect, the invention provides a method of operating a ferroelectric memory including a memory cell comprising a transistor having a first source/drain and a capacitor having a first electrode and a second electrode, with the first electrode connected to the source/drain of the transistor to create a node that is isolated when the transistor is off, the method comprising the step of: directly electrically connecting the isolated node and the second electrode of the capacitor at a predetermined time to essentially equalize the voltages on the first and second electrodes of the capacitor at the predetermined time. Preferably, the memory includes a bit line, a word line, and a plate line, the transistor includes a second source/drain and a gate, the bit line is connected to the second source drain, the word line is connected to the gate, and the plate line is connected to the second electrode, and the method further comprises: performing a write/rewrite cycle on the memory cell, including the step of raising the voltage on the word line; and, at the end of the write/rewrite cycle, adjusting the voltage on the bit line to the same voltage as the voltage on the plate line. Preferably, the memory includes a supply voltage power source having an output voltage, a shunt transistor including a gate, and a shunt line connected to the gate of the shunt transistor, and further comprising the steps of applying a voltage to the shunt line that is higher than the output voltage. Preferably, the memory cell includes two of the transistors, two of the capacitors, and two of the isolated nodes, and the step of directly electrically connecting includes the step of directly electrically connecting the isolated nodes.
In yet another aspect, the invention provides a method of operating a ferroelectric memory cell comprising a first transistor having a first source/drain and a second transistor having a second source/drain, a first capacitor having a first pair of electrodes and second capacitor having a second pair of electrodes, one of the first pair of electrodes connected to the first source/drain of the first transistor to create a first node that is isolated when the first transistor is off, and one of the second pair of electrodes connected to the second source/drain of the second transistor to create a second node that is isolated when the second transistor is off, the method comprising the step of directly electrically connecting the first isolated node and the second isolated node to essentially equalize the voltages on the nodes.
The invention also provides a method of manufacturing a ferroelectric memory comprising a transistor having a gate and source/drain, a word line connected to the gate, a capacitor having a first electrode and a second electrode with the first electrode connected to the source/drain of the transistor to create a node that is isolated when the transistor is off, and a shunt for directly electrically connecting the second electrode and the isolated node, the method comprising the steps of: fabricating a word line by forming a conductive layer and patterning the conductive layer; and at the same time and in the same process steps as the step of fabricating the word line, fabricating the shunt line. Preferably, the method further includes the steps of: fabricating a connector between the first electrode and the source/drain; and at the same time and in the same process steps as the step of fabricating a connector, fabricating a connector between the node and the second electrode.
The shunt circuit according to the invention may be used advantageously in combination with each of the prior art circuits discussed above as well as with any other memory cell circuit that includes an isolated node. In combination with the circuits utilizing a refresh scheme, such as that discussed in the Koike et al. reference, it results in simpler peripheral circuitry, a smaller total chip area, and a shorter overall cycle times. In combination with circuits utilizing a driven plate line, such as discussed in the Sumi et al. reference and U.S. Pat. No. 4,873,664, it results in faster access times and prevents disturb of the memory cell. In combination with fixed plate voltage schemes, such as that of U.S. Pat. No. 5,038,323 referenced above, it prevents the disturb caused by the leakage from the TC node. Further, the solution is relatively simple and economical to manufacture. Numerous other features, objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.